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? semiconductor components industries, llc, 2014 october, 2014 ? rev. 6 1 publication order number: ncn6001/d ncn6001 compact smart card interface ic the ncn6001 is an integrated circuit dedicated to the smart card interface applications. the device handles any type of smart card through a simple and flexible microcontroller interface. on top of that, thanks to the built?in chip select pin, several couplers can be connected in parallel. the device is particularly suited for low cost, low power applications, with high extended battery life coming from extremely low quiescent current. features ? 100% compatible with iso 7816?3, emv and gie?cb standards ? fully gsm compliant ? wide battery supply voltage range: 2.7 < v cc < 5.5 v ? programmable crd_vcc supply handles 1.8 v, 3.0 v or 5.0 v card operation ? programmable rise and fall card clock slopes ? programmable card clock divider ? built?in chip select logic allows parallel coupling operation ? esd protection on card pins (8.0 kv, human body model) ? supports up to 40 mhz input clock ? built?in programmable crd_clk stop function handles run or low state ? programmable crd_clk slopes to cope with wide operating frequency range ? fast crd_vcc turn?on and turn?of f sequence ? these are pb?free devices typical applications ? e?commerce interface ? automatic teller machine (atm) smart card ? point of sales (pos) system ? pay tv system www.onsemi.com tssop?20 dtb suffix case 948e marking diagram 20 1 ncn 6001 alyw 1 a = assembly location l = wafer lot y = year w = work week = pb?free package (note: microdot may be in either location) see detailed ordering and shipping information in the package dimensions section on page 32 of this data sheet. ordering information pin connections 1 2 3 4 5 6 7 8 20 19 18 16 15 14 13 (top view ) clk_spi i/o int clk_in mosi en_rpu miso cs lout_h gnd crd_vcc crd_clk crd_io 9 10 11 12 17 v cc lout_l pwr_gnd crd_rst crd_det c8/s1 c4/s0
ncn6001 http://onsemi.com 2 12 13 20 18 gnd l1 22 h 9 1 2 3 4 5 7 8 6 10 19 17 16 15 14 11 swa swb c8 c4 clk rst v cc gnd i/o 17 18 7 4 3 2 1 5 8 smartcard_c iso7816 gnd gnd gnd ncn6001 10 f u1 figure 1. typical application clk_spi clk_in mosi en_rpu miso cs lout_h gnd crd_vcc crd_clk crd_io lout_l crd_rst crd_det c8/s1 c4/s0 v cc i/o int v cc pwr_gnd gnd c2 10 f j1 c1 microcontroller v cc r1 47 k crd_det ground 3 9 1 2 6 10 5 8 7 15 11 19 17 16 12 en_rpu mosi clk_spi cs miso i/o int clk_in lout_h lout_l pwr_gnd crd_vcc clock divider 4 interrupt block dc/dc converter gnd 13 14 figure 2. block diagram programmable card detection 18 dual 8?bit shift register v cc address decoding logic control iso7816 sequencer card pins driver 20 c4/s0 c8/s1 crd_rst crd_clk crd_io b7 b6 b5 b4 b3 b2 b1 b0 b3 b2 b7 b6 b5 b4 b1 b0 gnd 20 k v cc 50 k crd_vcc 20 k v cc 500 k 3 states
ncn6001 http://onsemi.com 3 pin functions and description tssop name type description 1 i/o input/output pullup this pin is connected to an external microcontroller interface. a bidirectional level translator adapts the serial i/o signal between the smart card and the microcontroller. the level translator is enabled when cs = l, the sub address has been selected and the system operates in the asynchronous mode. when a synchronous card is in use, this pin is disconnected and the data and the transaction take place with the miso b3 register. the internal pullup resistor connected on the c side is activated and visible by the selected chip only. 2 int output pullup this pin is activated low when a card has been inserted and detected by crd_det pin. similarly, an interrupt is generated when the crd_vcc output is overloaded, or when the card has been extracted whatever be the transaction status (running or standby). the int signal is reset to high according to table 7 and figure 10. on the other hand, the pin is forced to a logic high when the input voltage v cc drops below 2.0 v. 3 clk_in clock input high impedance the built?in schmitt trigger receiver makes this pin suitable for a large type of clock signal (figure 29). this pin can be connected to either the microcontroller master clock, or to a crystal signal, to drive the external smart cards. the signal is fed to the internal clock selector circuit and translated to the crd_clk pin at either the same frequency, or divided by 2 or 4, depending upon the programming mode. note: the chip guarantees the emv 50% duty cycle when the clock divider ratio is 1/2 or 1/4 , even when the clk_in signal is out of the 45% to 55% range specified by iso and emv specifications. care must be observed, at pcb level, to minimize the pick?up noise coming from the clk_in line. 4 mosi input master out slave in: spi data input from the external microcontroller. this byte contents the address of the selected chip among the four possible, together with the programming code for a given interface. 5 clk_spi input clock signal to synchronize the spi data transfer. the built?in schmitt trigger receiver makes this pin compatible with a wide range of input clock signal (figure 29). this clock is fully independent from the clk_in signal and does not play any role with the data transaction. 6 en_rpu input, logic this pin is used to activate the i/o internal pullup resistor according to the here below true table: en_rpu = low i/o pullup resistor disconnected en_rpu = high i/o pullup resistor connected when two or more ncn6001 chips shares the same i/o bus, one chip only shall have the internal pullup resistor enabled to avoid any overload of the i/o line. moreover, when asynchronous and synchronous cards are handled by the interfaces, the activated i/o pullup resistor must preferably be the one associated with the asynchronous circuit . on the other hand, since no internal pullup bias resistor is built in the chip, pin 6 must be connected to the right voltage level to make sure the logic function is satisfied. 7 miso output master in slave out: spi data output from the ncn6001. this byte carries the state of the interface, the serial transfer being achieved according to the programmed mode (table 2), using the same clk_spi signal and during the same mosi time frame. the three high bits [b7:b5] have no meaning and shall be discarded by the microcontroller. an external 4.7 k pull down resistor might be necessary to avoid misunderstanding of the pin 7 voltage during the high z state. 8 cs input this pin synchronizes the spi communication and provides the chip address and selected functions. all the ncn6001 functions, both programming and card transaction, are disabled when cs = h. 9 v cc power this pin is connected to the ncn6001 supply voltage and must be bypassed to ground by a10 f/6.0 v capacitor. since tantalum capacitors have relative high esr, using low esr ceramic type (murata x5r, resr < 100 m ) is highly recommended. 10 lout_l power the low side of the external inductor is connected between this pin and pin 12 to provide the dc/dc function. the current flowing into this inductor is internally sensed and no external shunt resistor is used. typically, lout = 22 h, with dsr < 2.0 , yields a good efficiency performance for a maximum 65 ma dc output load. note: the inductor shall be sized to handle the 450 ma peak current flowing during the dc/dc operation (see coilcraft manufacturer data sheet).
ncn6001 http://onsemi.com 4 pin functions and description (continued) tssop description type name 11 pwr_gnd power this pin is the power ground associated with the built?in dc/dc converter and must be connected to the system ground together with ground pin 16. using good quality ground plane is recommended to avoid spikes on the logic signal lines. 12 lout_h power the high side of the external inductor is connected between this pin and pin 10 to activate the dc/dc function. the built?in nmos and pmos devices provide the switching function together with the crd_vcc voltage rectification (figure 16). 13 crd_vcc power this pin provides the power to the external card. it is the logic level ?1? for crd_io, crd_rst, crd_c4, crd_c8 and crd_clk signals. the energy stored by the dc/dc external inductor lout must be smoothed by a 10 f/low esr capacitor, connected across crd_vcc and gnd. using ceramic type of capacitor (murata x5r, esr < 50 m ) is strongly recommended. in the event of a crd_vcc u vlow voltage, the ncn6001 detects the situation and feedback the information in the status bit. the device does not take any further action, particularly the dc/dc converter is neither stopped nor re programmed by the ncn6001. it is up to the external mpu to handle the situation. however, when the crd_vcc is overloaded, the ncn6001 shuts off the dc/dc converter, runs a power down iso sequence and reports the fault in the status register. since high transient current flows from this pin to the load, care must be observed, at pcb level, to minimize the series esr and esl parasitic values. the ncn6001 demo board provides an example of a preferred pcb layout. 14 c8/s1 i/o auxiliary mixed analog/digital line to handle either a synchronous card, or as chip select identification (miso, bit 0): see figure 8. the pin is driven by an open drain stage, the pullup resistor being connected to the crd_vcc supply. when the pin is used as a logic input (asynchronous cards), the positive logic condition applies: connected to gnd logic = zero connected to v cc or left open logic = one a built?in accelerator circuit makes sure the output positive going rise time is fully within the iso/emv specifications. note: the pin is capable of reading the logic level when the chip operates an asynchronous interface, but is not intended to read the data from the external card when operated in the synchronous mode. it merely returns the logic state forced during a write instruction to the card. 15 c4/s0 i/o auxiliary mixed analog/digital line to handle either a synchronous card, or as chip select identification (miso, bit 1): see figure 8. the pin is driven by an open drain stage, the pullup resistor being connected to the crd_vcc supply. when the pin is used as a logic input (asynchronous cards), the positive logic condition applies: connected to gnd logic = zero connected to v cc or left open logic = one a built?in accelerator circuit makes sure the output positive going rise time is fully within the iso/emv specifications. note: the pin is capable of reading the logic level when the chip operates an asynchronous interface, but is not intended to read the data from the external card when operated in the synchronous mode. it merely returns the logic state forced during a write instruction to the card. 16 gnd signal the logic and low level analog signals shall be connected to this ground pin. this pin must be externally connected to the pwr_gnd pin 12. the designer must make sure no high current transients are shared with the low signal currents flowing into this pin. 17 crd_clk output this pin is connected to the clk pin of the card connector. the crd_clk signal comes from the clock selector circuit output. an internal ac tive pull down nmos device forces this pin to ground during either the crd_vcc startup sequence, or when crd_vcc = 0 v. the rise and fall slopes, either fast or slow, of this signal can be programmed by the mosi message (table 2). care must be observed, at pcb level, to minimize the pick?up noise coming from the crd_clk line.
ncn6001 http://onsemi.com 5 pin functions and description (continued) tssop description type name 18 crd_det input the signal coming from the external card connector is used to detect the presence of the card. a built?in pullup low current source biases this pin high, making it active low, assuming one side of the external switch is connected to ground. a built?in digital filter protect the system against voltage spikes present on this pin. the polarity of the signal is programmable by the mosi message, according to the logic state depicted table 2. on the other hand, the meaning of the feedback message contained in the miso register bit b4, depends upon the spi mode of operation as defined here below: spi normal mode: the miso bit b4 is high when a card is inserted, whatever be the polarity of the card detect switch. spi special mode: the miso bit b4 copies the logic state of the card detect switch as depicted here below, whatever be the polarity of the switch used to handle the detection: crd_det = low miso/b4 = low crd_det = high miso/b4 = high in both cases, the chip must be programmed to control the right logic state (table 2). since the bias current supplied by the chip is very low, typically 5.0 a, care must be observed to avoid low impedance or cross coupling when this pin is in the open state. 19 crd_rst output this pin is connected to the reset pin of the card connector. a level translator adapts the reset signal from the microcontroller to the external card. the output current is internally limited to 15 ma. the crd_rst is validated when cs = low and hard wired to ground when the card is deactivated, by and internal active pull down circuit. care must be observed, at pcb design level, to avoid cross coupling between this signal and the crd_clk clock. 20 crd_io i/o pullup this pin handles the connection to the serial i/o pin of the card connector. a bidirectional level translator adapts the serial i/o signal between the card and the microcontroller. an internal active pull down mos device forces this pin to ground during either the crd_vcc startup sequence, or when crd_vcc = 0 v. the crd_io pin current is internally limited to 15 ma. care must be observed, at pcb design level, to avoid cross coupling between this signal and the crd_clk clock.
ncn6001 http://onsemi.com 6 maximum ratings (t a = +25 c unless otherwise noted) rating symbol value unit power supply voltage v cc 6.0 v power supply current note: this current represents the maximum peak current the pin can sustain, not the ncn6001 average consumption. i bat 500 ma power supply current i cc 150 (internally limited) ma digital input pins v in ?0.5 v < v in < v cc +0.5 v, but < 6.0 v v digital input pins i in 5.0 ma digital output pins v out ?0.5 v < v in < v cc +0.5 v, but < 6.0 v v digital output pins i out 10 ma card interface pins v card ?0.5 v < v card < crd_vcc +0.5 v v card interface pins, excepted crd_clk i card 15 (internally limited) ma inductor current i lout 500 (internally limited) ma esd capability (note 1) standard pins card interface pins crd_det v esd 2.0 8.0 4.0 kv kv kv power dissipation @ tamb = +85 c thermal resistance, junction?to?air (r ja ) p ds r ja 320 125 mw c/w operating ambient temperature range t a ?25 to +85 c operating junction temperature range t j ?25 to +125 c maximum junction temperature (note 2) t jmax +150 c storage temperature range t stg ?65 to +150 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. human body model, r = 1500 , c = 100 pf. 2. absolute maximum rating beyond which damage to the device may occur.
ncn6001 http://onsemi.com 7 digital parameters @ 2.7 v < v cc < 5.5 v (?25 c to +85 c ambient temperature, unless otherwise noted). note: digital inputs undershoot < ? 0.3 v to ground, digital inputs overshoot < 0.3 v to v cc . rating pin symbol min typ max unit input asynchronous clock duty cycle = 50% @ v cc = 3.0 v over the temperature range @ v cc = 5.0 v over the temperature range 3 f clkin ? ? ? ? 30 40 mhz input clock rise time input clock fall time 3 f tr f tf 2.5 2.5 ? ? ? ? ns ns input spi clock 5 f clkspi ? ? 15 mhz input clk_spi rise/fall time @ cout = 30 pf 5 tr spi , tf spi ? ? 12 ns input mosi rise/fall time @ cout = 30 pf 4 tr mosi , tf mosi ? ? 12 ns output miso rise/fall time @ cout = 30 pf 7 tr miso , tf miso ? ? 12 ns input cs rise/fall time 8 tr str , tf str ? ? 12 ns i/o data transfer switching time, both directions (i/o and crd_io), @ cout = 30 pf i/o rise time * (note 4) i/o fall time 1, 20 t rio t fio ? ? ? ? 0.8 0.8 s s int pullup resistance 2 r ita 20 50 80 k positive going input high voltage threshold (clk_in, mosi, clk_spi, en_rpu, cs ) 2, 3, 4, 5, 6, 8 v ia 0.70 * v cc ? v cc v negative going input high voltage threshold (clk_in, mosi, clk_spi, en_rpu, cs ) 2, 3, 4, 5, 6, 8 v illa 0 ? 0.3 * v cc v output high voltage int , miso @ o h = ?10 a 2, 7 v oh v cc ?1.0 v ? v cc v output low voltage int , miso @ o h = 200 a 2, 7 v ol ? ? 0.4 v delay between two consecutive clk_spi sequence 5 td clk 33 ? ? ns product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. since a 20 k (typical) pullup resistor is provided by the ncn6001, the external mpu can use an open drain connection. on the other hand, nmos smart cards can be used straightforward.
ncn6001 http://onsemi.com 8 power supply @ 2.7 v < v cc < 5.5 v (?25 c to +85 c ambient temperature, unless otherwise noted). rating pin symbol min typ max unit input power supply 9 v cc 2.70 ? 5.50v v standby supply current conditions: int = clk_in = clk_spi = cs = h i/o = mosi = en_rpu = h, no card inserted v cc = 3.0 v v cc = 5.0 v 9 icc sb ? ? 25 35 50 60 dc operating current clk_in = low, all card pins unloaded @ v cc = 3.3 v, crd_vcc = 5.0 v @ v cc = 5.5 v, crd_vcc = 5.0 v 9 icc op ? ? ? ? 0.5 1.5 ma v cc under voltage detection high v cc under voltage detection low v cc under voltage (note 6) 9 vcc lh vcc ll vcc por 2.20 2.00 1.50 ? ? ? 2.70 2.60 2.20 v output card supply voltage @ 2.7 v < v cc < 5.5 v crd_vcc = 1.8 v @ iload = 35 ma crd_vcc = 3.0 v @ iload = 60 ma crd_vcc = 5.0 v @ iload = 65 ma 13 v c2h v c3h v c5h 1.65 2.75 4.75 ? 1.80 3.00 5.00 1.95 3.25 5.25 v maximum continuous output current @ crd_vcc = 1.8 v @ crd_vcc = 3.0 v @ crd_vcc = 5.0 v 13 icc 35 60 65 ? ? ? ? ? ? ma output over current limit v cc = 3.3 v, crd_vcc = 1.8 v, 3.0 v or 5.0 v v cc = 5.0 v, crd_vcc = 1.8 v, 3.0 v or 5.0 v 13 iccov ? ? 100 150 ? ? ma output dynamic peak current @ crd_vcc = 1.8 v, 3.0 v or 5.0 v, cout = 10 f (notes 4 and 5) 13 iccd 100 ? ? ma output card supply voltage ripple @ v cc = 3.6 v, lout = 22 h, cout1 = cout2 = 4.7 f ceramic x7r, iout = 55 ma crd_vcc = 5.0 v crd_vcc = 3.0 v (note 4) crd_vcc = 1.8 v 13 ? ? ? ? 35 35 35 ? ? ? mv output card supply turn on time @ lout = 22 f, cout1 = 10 f ceramic v cc = 2.7 v, crd_vcc = 5.0 v 13 vcc ton ? ? 500 s output card supply shut off time @ cout1 = 10 f, ceramic v cc = 2.7 v, crd_vcc = 5.0 v, vcc off < 0.4 v 13 vcc toff ? 100 250 s 4. ceramic x7r, smd type capacitors are mandatory to achieve the crd_vcc specifications. when an electrolytic capacitor is used, the external filter must include a 220 nf, max 50 m esr capacitor in parallel, to reduce both the high frequency noise and ripple to a minimum. depending upon the pcb layout, it might be necessary to use two 4.7 f/6.0 v/ceramic/x5r/smd 0805 in parallel, yielding an improved crd_vcc ripple over the temperature range. 5. pulsed current, according to iso7816?3, paragraph 4.3.2. 6. no function externally available during the v cc por sequence.
ncn6001 http://onsemi.com 9 smart card interface @ 2.7 v < v cc < 5.5 v (?25 c to +85 c ambient temperature, unless otherwise noted). note: digital inputs undershoot < ?0.3 v to ground, digital inputs overshoot < 0.3 v to v cc . rating pin symbol min typ max unit crd_rst @ crd_vcc = 1.8 v, 3.0 v, 5.0 v output reset v oh @ irst = ?200 a output reset v ol @ irst = 200 a output reset rise time @ cout = 30 pf output reset fall time @cout = 30 pf 19 v oh v ol t r t f crd_vcc ? 0.5 0 ? ? ? ? ? ? crd_vcc 0.4 100 100 v v ns ns crd_clk as a function of crd_vcc crd_vcc = +5.0 v or 3.0 v or 1.8v output frequency output v oh @ icrd_clk = ?200 a output v ol @ icrd_clk = 200 a crd_clk output duty cycle crd_vcc = 5.0 v crd_vcc = 3.0 v crd_vcc = 1.8 v (note 7) rise & fall time @ crd_vcc = 1.80 v to 5.0 v fast mode output crd_clk rise time @ cout = 30 pf output crd_clk fall time @ cout = 30 pf rise & fall time @ crd_vcc = 1.80 v to 5.0 v slow mode output crd_clk rise time @ cout = 30 pf output crd_clk fall time @ cout = 30 pf 17 f crdclk v oh v ol f crddc t ress t fcs t rills t ulsa ? crd_vcc ? 0.5 0 45 40 40 ? ? ? ? 2.1 1.9 11.5 10.8 20 crd_vcc +0.4 55 60 60 4 4 16 16 mhz v v % % % ns ns ns ns crd_io @ crd_vcc = 1.8 v 3.0 v, 5.0 v crd_io data transfer frequency crd_io rise time @ cout = 30 pf crd_io fall time @ cout = 30 pf output v oh @ icrd_clk = ?20 a output v ol @ icrd_clk = 500 a, v il = 0 v 20 f io t rio t fio v oh v ol ? ? ? crd_vcc ? 0.5 0 400 ? ? ? ? ? 0.8 0.8 crd_vcc 0.4 khz s s v v crd_io pullup resistor 20 r crdpu 14 20 26 k crd_c8 output rise and fall time @ cout = 30 pf 14 t rc8, t fc8 ? ? 100 ns crd_c4 output rise and fall time @ cout = 30 pf 15 t rc4, t fc4 ? ? 100 ns crd_c4 and crd_c8 data transfer frequency 14, 15 f c48 ? 400 ? khz crd_c8, crd_c4 output voltages high level @ irst = ?200 a low level @ irst = +200 a 14, 15 v oh, v ol crd_vcc ? 0.5 0 ? ? ? 0.4 v v c8/s0 and c4/s0 address bias current (note 8) 14, 15 i bc4c8 ? 1.0 ? a card detection digital filter delay: card insertion card extraction 18 t crdin t crdoff 25 25 50 50 150 150 s s card insertion or extraction positive going input high voltage 18 v ihdet 0.70 * v cc ? v cc v card insertion or extraction negative going input low voltage 18 v ildet 0 ? 0.30 * v cc v card detection bias pullup current @ v cc = 5.0 v 18 i det ? 10 ? a output peak max current under card static operation mode @ crd_vcc = 3.0 v or = 5.0 v crd_rst, crd_io, crd_c4, crd_c8 1, 20 icrd_iorst ? ? 15 ma output peak max current under card static operation mode @ crd_vcc = 3.0 v or = 5.0 v crd_clk 17 icrd_clk ? ? 70 ma 7. parameter guaranteed by design, function 100% production tested. 8. depending upon the environment, using and external pullup resistor might be necessary to cope with pcb surface leakage curren t.
ncn6001 http://onsemi.com 10 programming write register wrt_reg the wrt_reg register handles three command bits [b5:b7] and five data bits [b0:b4] as depicted in table 1. these bits are concatenated into a single byte to accelerate the programming sequence. the register can be updated when cs is low only. the crd_rst pin reflects the content of the mosi wrt_reg[b4] during the chip programming sequence. since this bit shall be low to address the internal register of the chip, care must be observed as this signal will be immediately transferred to the crd_rst pin. table 1. wrt_reg bits definitions b0, b1 if (b7 + b6 + b5) <> 110 and (b7 + b6 + b5) <> 101 and (b7 + b6 + b5) <> 111 then case 00 crd_vcc = 0 v case 01 crd_vcc = 1.8 v case 10 crd_vcc = 3.0 v case 11 crd_vcc = 5.0 v else if (b7 + b6 + b5) = 110 then b1 drives c4 b0 drives c8 else if (b7 + b6 + b5) = 101 then case (b4 + b3 + b2 + b1 + b0) = 0000 crd_det = no case (b4 + b3 + b2 + b1 + b0) = 0001 crd_det = nc case (b4 + b3 + b2 + b1 + b0) = 0010 spi_mode = special case (b4 + b3 + b2 + b1 + b0) = 0011 spi_mode = normal end if b2, b3 if (b7 + b6 + b5) <> 110 and (b7 + b6 + b5) <> 101 and (b7 + b6 + b5) <> 111 then case 00 crd_clk = l case 01 crd_clk = clk_in case 10 crd_clk = clk_in/2 case 11 crd_clk = clk_in/4 else if (b7 + b6 + b5) = 110 then b3 drives crd_clk b2 drives crd_io else if (b7 + b6 + b5) = 101 then case (b4 + b3 + b2 + b1 + b0) = 0000 crd_det = no case (b4 + b3 + b2 + b1 + b0) = 0001 crd_det = nc case (b4 + b3 + b2 + b1 + b0) = 0010 spi_mode = special case (b4 + b3 + b2 + b1 + b0) = 0011 spi_mode = normal end if b4 drives crd_rst pin (note 10) b5, b6, b7 000 select asynchronous card #0 (note 9), four chips bank cs signal 001 select asynchronous card #1 (note 9), four chips bank cs signal 010 select asynchronous card #2 (note 9), four chips bank cs signal 011 select asynchronous card #3 (note 9), four chips bank cs signal 100 select external asynchronous card, dedicated cs signal 110 select external synchronous card, dedicated cs signal 101 set card detection switch polarity, set spi_mode normal or special. set crd_clk slopes fast or slow. 111 reserved for future use 9. when operating in asynchronous mode, [b5:b7] are compared with the external voltage levels present pins c4/s0 and c8/s1 (resp ectively pins 15 and 14). 10. the crd_rst pin reflects the content of the mosi wrt_reg[b4] during the chip programming sequence. since this bit shall be l ow to address the internal register of the chip, care must be observed as this signal will be immediately transferred to the crd_rst pin.
ncn6001 http://onsemi.com 11 table 2. wrt_reg bits definitions and functions address parameters chip bank mosi bits [b3:b2] mosi bits [b1:b0] mosi bits [b7:b0] 1 b7 b6 b5 b4 b3 b2 b1 b0 crd_clk crd_vcc crd_det 1 0 x x rst 0 0 0 0 low 0 ? 1 0 x x rst 0 1 0 1 1/1 1.8 v ? 1 0 x x rst 1 0 1 0 1/2 3.0 v ? 1 0 x x rst 1 1 1 1 1/4 5.0 v ? 1 1 0 1 0 0 0 0 0 ? ? no 1 1 0 1 0 0 0 0 1 ? ? nc 1 1 0 1 0 0 0 1 0 ? ? special 1 1 0 1 0 0 0 1 1 ? ? normal 1 1 0 1 0 0 1 0 0 ? ? slo_slp 1 1 0 1 0 0 1 0 1 ? ? fst_slp 1 1 1 1 ? ? ? ? ? ? ? rfu 2 1 0 0 rst 0 0 0 0 low 0 ? 2 1 0 0 rst 0 1 0 1 1/1 1.8 v ? 2 1 0 0 rst 1 0 1 0 1/2 3.0 v ? 2 1 0 0 rst 1 1 1 1 1/4 5.0 v ? 2 1 1 0 rst clk i/o c4 c8 ? ? data to sync. card 2 1 0 1 0 0 0 0 0 ? ? no 2 1 0 1 0 0 0 0 1 ? ? nc 2 1 0 1 0 0 0 1 0 ? ? special 2 1 0 1 0 0 0 1 1 ? ? normal 2 1 0 1 0 0 1 0 0 ? ? slo_slp 2 1 0 1 0 0 1 0 1 ? ? fst_slp 2 1 1 1 ? ? ? ? ? ? ? rfu 11. chip bank 1 = asynchronous cards, four slots addresses 1 to 4. chip bank 2 = asynchronous or synchronous card, single slot. 12. address 101 and bits [b0 : b4] not documented in the table are reserved for future use. address 111 is reserved for future use. although using the %111xxxxx code is harmless from a ncn6001 silicon standpoint, care must be observed to avoid uncontrolled operation of the interface sharing the same digital bus. when this code is presented on the digital bus, the crd_rst signal of any interface sharing the cs signal, immediately reflects the digital content of the mosi bit b4 register. similarly, the miso register of the shared interface is presented on the spi port. consequently, data collision, at miso level, and uncontrolled card operation are likely to happen if the system uses a common chip select line. it is strongly recommended to run a dedicated cs bit to any external circuit intended to use the $111xxxxx code. on the other hand, the crd_rst signal will be forced to low when the internal register of the chip is programmed to accommodate different hardware conditions (no/nc, special/normal, slo_slp/fst_slp). generally speaking, such a configuration shall take place during the power on reset to avoid crd_rst activation.
ncn6001 http://onsemi.com 12 read register read_reg the read_reg register contains the data read from the interface and from the external card. the selected register is transferred to the miso pin during the mosi sequence (cs = low). table 3 gives the bits definition. depending upon the programmed spi_mode, the content of read_reg is transferred on the miso line either on the positive going (spi_mode = special) or upon the negative going slope (spi_mode = normal) of the clk_spi signal. the external microcontroller shall discard the three high bytes since they carry no valid data. table 3. mosi and miso bits identifications and functions mosi b7 b6 b5 b4 b3 b2 b1 b0 operating mode 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 0 rst rst rst rst rst rst clk clk clk clk clk clk clk clk clk clk clk i/o v cc v cc v cc v cc v cc c4 v cc v cc v cc v cc v cc c8 asynchronous, program chip asynchronous, program chip asynchronous, program chip asynchronous, program chip asynchronous, program chip synchronous, sets card bits miso z z z card detect i/o c4 c8 pwr monitor read back data asynchronous mode in this mode, the crd_c4 and crd_c8 pins are used to define the physical addresses of the interfaces when a bank of up to four ncn6001 share the same digital bus. synchronous mode in this mode, crd_c4 and crd_c8 are connected to the smart card and it is no longer possible to share the cs signal with other device. consequently, a dedicated chip select signal must be provided when the interfaces operate in a multiple operation mode (figure 33). on the other hand, since bits [b4 ? b0] of the mosi register contain the smart card data, programming the crd_vcc output voltage shall be done by sending a previous mosi message according to table 1 and table 2. the crd_rst pin reflects the content of the mosi wrt_reg[b4] during the chip programming sequence. since this bit shall be low to address the internal register of the chip, care must be observed as this signal will be immediately transferred to the crd_rst pin. since no physical address can exist when the chip operates in this mode, the mosi register must use the format %100xxxxx to program the chip (%100 prefix, xxxxx data). example: ldaa #%10010111 ;set rst = h, clk = 1/1, vcc = 5.0 v staa mosi ldaa #%11010011 ;sync. card: set rst = h, clk = l, io = l, c4 = h, c8= h staa mosi ldaa #%001 11110 ;async. card: set rst = h, clk = ? , vcc = 3.0 v staa mosi
ncn6001 http://onsemi.com 13 startup default conditions at startup, when the v cc power supply is turned on, the internal por circuit sets the chip in the default conditions as defined in table 4. table 4. startup default conditions crd_det normally open crd_vcc off crd_clk t r and t f = slow crd_clk low protocol special mode card detection the card is detected by the external switch connected pin 18. the internal circuit provides a positive bias of this pin and the polarity of the insertion/extraction is programmable by the mosi protocol as depicted in table 2. the bias current is 1.0 a typical and care must be observed to avoid leakage to ground from this pin to maintain the logic function. in particular, using a low impedance probe (< 1.0 m ) may lead to uncontrolled operation during the debug. depending upon the programmed condition, the card can be detected either by a normally open (default condition) or a normally close switch (table 2). on the other hand, the meaning of the feedback message contained in the miso register bit b4, depends upon the spi mode of operation as defined here below: spi normal mode: the miso bit b4 is high when a card is inserted, whatever be the polarity of the card detect switch. spi special mode: the miso bit b4 copies the logic state of the card detect switch as depicted here below, whatever be the polarity of the switch used to handle the detection: crd_det = low miso/b4 = low crd_det = high miso/b4 = high crd_vcc operation the built?in dc/dc converter provides the crd_vcc voltage and can be programmed to run one of the three possible values, 1.8 v, 3.0 v or 5.0 v, assuming the input voltage v cc is within the 2.7 v to 5.5 v range. in any case, crd_vcc is voltage regulated, together with a current overload detection. on the other hand, the power conversion is automatically switched to handle either a boost or a buck mode of operation, depending upon the difference between the input voltage v cc and the output supply crd_vcc. the crd_vcc output current is a function of the v cc input value as depicted in table 5. table 5. crd_vcc output voltage range crd_vcc comments 1.80 v maximum output dc current = 35 ma 3.0 v maximum output dc current = 60 ma 5.0 v maximum output dc current = 65 ma whatever the crd_vcc output voltage may be, a built?in comparator makes sure the voltage is within the iso7816?3/ emv specifications. if the voltage is no longer within the minimum/maximum values, the dc/dc is switched off, the power down sequence takes place and an interrupt is presented at the int pin 2. powerup sequence the powerup sequence makes sure all the card related signals are low during the crd_vcc positive going slope. these lines are validated when crd_vcc is above the minimum specified voltage (depending upon the programmed crd_vcc value). figure 3. typical startup crd_vcc sequence
ncn6001 http://onsemi.com 14 at powerup, the crd_vcc voltage rise time depends upon the current capability of the dc/dc converter associated with the external inductor l1 and the reservoir capacitor connected across crd_vcc and ground. during this sequence, the average input current is 300 ma typical (figure 3), assuming the system is fully loaded during the startup. finally, the application software is responsible for the smart card signal sequence. on the other hand, at turn off, the crd_vcc fall time depends upon the external reservoir capacitor and the peak current absorbed by the internal nmos transistor built across crd_vcc and ground. these behaviors are depicted in figure 4. since these parameters have finite values, depending upon the external constraints, the designer must take care of these limits if the t on or the t off provided by the data sheets does not meet his requirements. figure 4. crd_vcc typical rise and fall time figure 5. startup sequence with atr
ncn6001 http://onsemi.com 15 power down sequence the ncn6001 provides an automatic power down sequence, according to the iso7816?3 specifications, and the communication session terminates immediately. the sequence is launched when the card is extracted, or when the crd_vcc voltage is overloaded as described by the iso/cei 7816?3 sequence depicted hereafter: iso7816?3 sequence: force rst to low force clk to low, unless it is already in this state force c4 & c8 to low force crd_io to low shut off the crd_vcc supply since the internal digital filter is activated for any card insertion or extraction, the physical power sequence will be activated 50 s (typical) after the card has been extracted. of course, such a delay does not exist when the mpu intentionally launches the power down. figure 6 shows the oscillogram captured in the ncn6001 demo board. the internal active pull down nmos connected across crd_vcc and gnd discharges the external reservoir capacitor in 100 s (typical), assuming cout = 10 f. figure 6. typical power down sequence typical delay between each signal is 500 ns the internal active pull down nmos connected across crd_vcc and gnd discharges the external reservoir capacitor in 100 s (typical), assuming cout = 10 f.
ncn6001 http://onsemi.com 16 data i/o level shifter the level shifter accommodates the voltage difference that might exist between the microcontroller and the smart card. a pulsed accelerator built?in circuit provides the fast positive going transient according to the iso7816?3 specifications. the basic i/o level shifter is depicted in figure 7. logic and level shift q4 q3 q2 r2 18 k q5 gnd crd_vcc 13 crd_io 20 crd_vcc card enable por seq 1 200 ns 200 ns q1 r1 18 k en_rpu 6 i/o 1 v cc 9 v cc pmos u1 vcc q5 gnd sync mosi/b3 mosi/b2 from mosi decoding figure 7. basic i/o internal circuit the transaction is valid when the chip select pin is low, the i/o signal being open drain or totem pole on either sides. since the device can operate either in a single or a multiple card system, provisions have been made to avoid crd_io current overload. depending upon the selected mode of operation (async. or sync), the card i/o line is respectively connected to either i/o pin 1, or to the mosi register byte bit 2. on the other hand, the logic level present at the card i/o is feedback to the c via the miso register bit 3. the logic level present at pin 6 controls the connection of the internal pullup as depicted in table 6. table 6. i/o pullup resistor true table en_rpu i/o pullup resistor device operation low open, 18 k disconnected parallel mode high internal 18 k pullup active single device note: 18 k typical value figure 8. typical i/o rise and fall time note: both sides of the interface run with open drain load (worst case condition).
ncn6001 http://onsemi.com 17 general purpose crd_c4 and crd_c8 these two pins can be used as a logic input to define the address of a given interface (in the range $00 to $11), or as a standard c4/c8 access to the smart card?s channels. since these pins can be directly connected to the v cc power supply, both output stages are built with switched nmos/pmos totem pole as depicted in figure 9. figure 9. typical crd_c4 output drive and logic control q1 u3 u4 gnd 500 r r1 crd_vcc c4 q2 u1 level shifter v cc wrt_c4 gnd q3 esd switched bias u6 u9 i = 1 a control address read_c4 u5 u8 u7 v max 3 3 3 2 1 2 1 2 1 u2 v cc crd_vcc the c4 and c8 pins are biased by an internal current source to provide a logic one when the pin is left open. in this case, care must be observed to avoid relative low impedance to ground to make sure the pin is at a high logic level. however, it is possible to connect the pin to v cc (battery supply) to force the logic input to a high level, regardless of the input bias. thanks to the control internal signal, the system automatically adapts the mode of operation (chip address or data communication) and, except the leakage, no extra current is drawn from the battery to bias these pins when the logic level is high. when any of these pins is connected to gnd, a continuous 1 a typical sink current will be absorbed from the battery supply. the switched totem pole structure provides the fast positive going transient when the related pin is forced to the high state during a data transfer. in the event of a low impedance connected across c4 or c8 to ground, the current flow is limited to 15 ma, according to the iso7816?3 specification. the two general purpose pins can transfer data from the external microcontroller to the card and read back the logic state, but none of these pins can read the data coming from the external smart card. on the other hand, both c4 and c8 can read input logic, hence the physical address of a given chip. in order to sustain the 8 kv esd specified for these pins, an extra protection structure q3 has been implemented to protect the mos gates of the input circuit.
ncn6001 http://onsemi.com 18 interrupt when the system is powered up, the int pin is set to high upon por signal. the interrupt pin 2 is forced low when either a card is inserted/extracted, or when a fault is developed across the crd_vcc output voltage. this signal is neither combined with the cs signal, nor with the chip address. consequently, an interrupt is placed on the c input as soon as one of the condition is met. the int signal is clear to high upon one of the condition given in table 7. table 7. interrupt reset logic interrupt source cs crd_vcc chip address card insertion l > 0 selected chip mosi[b7 : b5] = 0xx or mosi[b7 : b5] = 101 card insertion l = 0 selected chip mosi[b7 :b5] = 0xx or mosi[b7 : b5] = 101 over load l = 0 selected chip mosi[b7 : b5] = 0xx or mosi[b7 : b5] = 101 when several interfaces share the same digital c bus, it is up to the software to pool the chips, using the miso register to identify the source of the interrupt. figure 10. basic interrupt function cs int crd_det mosi_b0 mosi_b1 crd_vcc > 0 v crd_vcc = 0 v over load crd_vcc t0 t2 t10 t3 t4 t9 t6 t7 t8 t5 t1 t11 1 2 3 table 8. interrupt reset logic operation t0 a card has been inserted into the reader and detected by the crd_det signal. the ncn6001 pulls down the interrupt line. t1 the c sets the cs signal to low, the chip is now active, assuming the right address has been placed by the mosi register. t2 the c acknowledges the interrupt and resets the int to high by the mosi [b1 : b0 ] logic state: crd_vcc is programmed higher than zero volt. t3 the card has been extracted from the reader, crd_det goes low and an interrupt is set (int = l). on the other hand, the pwr_down sequence is activated by the ncn6001. t4 the interrupt pin is clear by the zero volt programmed to the interface. t5 same as t0 t6 the c start the dc/dc converter, the interrupt is cleared (same as t2) t7 an overload has been detected by the chip : the crd_vcc voltage is zero, the int goes low. t8 the card is extracted from the reader, crd_det goes low and an interrupt is set (int = l). t9 the card is re?inserted before the interrupt is acknowledged by the c: the int pin stays low. t10 the c acknowledges the interrupt and reset the int to high by the mosi [b1 : b0 ] logic state: crd_vcc is programmed higher than zero volt. t11 the chip select signal goes high, all the related ncn6001 interface(s) are deactivated and no further programming or transaction can take place.
ncn6001 http://onsemi.com 19 spi port the product communicates to the external microcontroller by means of a serial link using a synchronous port interface protocol, the clk_spi being low or high during the idle state. the ncn6001 is not intended to operate as a master controller, but execute commands coming from the mpu. the clk_spi, the cs and the mosi signals are under the microcontroller?s responsibility. the miso signal is generated by the ncn6001, using the clk_spi and cs lines to synchronize the bits carried out by the data byte. the basic timings are given in figure 11 and figure 12. the system runs with two internal registers associated with the mosi and miso data: wrt_reg is a write only register dedicated to the mosi data. read_reg is a read only register dedicated to the miso data. figure 11. basic spi timings and protocol mpu asserts chip select ncn6001 reads bit mpu reads bit rst_counter mosi spi_clk cs miso tclr mpu enables clock mpu sends bit ncn6001 sends bit from read_reg when the cs line is high, no data can be written or read on the spi port. the two data lines becomes active when cs = low, the internal shift register is cleared and the communication is synchronized by the negative going edge of the cs signal. the data present on the mosi line is considered valid on the negative going edge of the clk_spi clock and is transferred to the shift register on the next positive edge of the same clk_spi clock. to accommodate the simultaneous miso transmit, an internal logic identifies the chip address on the fly (reading and decoding the three first bits) and validates the right data present on the line. consequently, the data format is msb first to read the first three signal as bits b5, b6 and b7. the chip address is decoded from this logic value and validates the chip according to the c4 and c8 conditions (figure 12). figure 12. chip address decoding protocol and miso sequence mpu asserts chip set miso line = high impedance address decode mosi spi_clk cs miso mpu enables clock b7 b6 b5 b4 b3 b2 b1 b0 lsb command and control chip address the chip address is decoded on the third clock pulse. the miso signal is activated and data transferred msb
ncn6001 http://onsemi.com 20 when the eight bits transfer is completed, the content of the internal shift register is latched on the positive going edge of the cs signal and the ncn6001 related functions are updated accordingly. figure 13. basic multi command spi bytes select chip from synchronous bank chip ny chip nx tdclk special mode: miso is synchronized with the spi_clk positive going slope normal mode: miso is synchronized with the spi_clk negative going slope miso line = high impedance miso line = high impedance b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 spi_clk cs mosi set_rst set_clk set_vcc address decode chip address command and control msb msb lsb lsb miso special mode miso normal mode mpu enables clock since the four chips present in the asynchronous bank have an individual physical address, the system can control several of these chips by sending the data content within the same cs frame as depicted in figure 13. the bits are decoded on the fly and the related sub blocks are updated accordingly. according to the spi general specification, no code or activity will be transferred to any chip when the cs is high. when two spi bytes are sequentially transferred on the mosi line, the clk_spi sequence must be separated by at least one half positive period of this clock (see td clk parameter). the oscillograms shown in figure 14 and figure 15 illustrate the spi communication protocol (source: ncn6001 demo board). figure 14. programming sequence, chip address = $03
ncn6001 http://onsemi.com 21 figure 15. miso read out sequences protocol: special mode protocol: standard spi dc/dc operation the power conversion is based on a full bridge structure capable to handle either step up or step down power supply (figure 16). the operation is fully automatic and, beside the output voltage programming, does not need any further adjustments. figure 16. basic dc/dc converter g_q4 g_q2 g_q7 g_hiz g_q3 g_q1 cmd_stop cmd_5.0v cmd_3.0v cmd_1.8v gnd gnd gnd 22 h l1 gnd 11 pwr_gnd 10 f c2 q2 q7 q4 q6 q5 q3 10 12 q1 10 f mixed logic/analog block v cc crd_vcc c1 13 6 in order to achieve the 250 s max time to discharge crd_vcc to 400 mv called by the emv specifications, an active pull down nmos is provided (q7) to discharge the external crd_vcc reservoir capacitor. this timing is guaranteed for a 10 f maximum load reservoir capacitor value (figure 4).
ncn6001 http://onsemi.com 22 the system operates with a two cycles concept (all comments are referenced to figure 16 and figure 17): 1 ? cycle 1 q1 and q4 are switched on and the inductor l1 is charged by the energy supplied by the external battery. during this phase, the pair q2/q3 and the pair q5/q6 are switched off. the current flowing the two mosfet q1 and q4 is internally monitored and will be switched off when the ipeak value (depending upon the programmed output voltage value) is reached. at this point, cycle 1 is completed and cycle 2 takes place. the on time is a function of the battery voltage and the value of the induct- or network (l and zr) connected across pins 10/11. a 4 s timeout structure ensures the system does run in a continuous cycle 1 loop 2 ? cycle 2 q2 and q3 are switched on and the energy stored into the inductor l1 is dumped into the external load through q2. during this phase, the pair q1/q4 and the pair q5/q6 are switched off. the current flow period is constant (900 ns typical) and cycle 1 repeats after this time if the crd_vcc voltage is below the specified value. when the output voltage reaches the specified value (1.8 v, 3.0 v or 5.0 v), q2 and q3 are switched off immediately to avoid over voltage on the output load. in the meantime, the two extra nmos q5 and q6 are switched on to fully discharge any current stored into the inductor, avoiding ringing and voltage spikes over the system. figure 17 illustrates the theoretical waveforms present in the dc/dc converter. crd_vcc charged figure 17. theoretical dc/dc operating waveforms i peak crd_vcc il q5/q6 q2/q3 q1/q4 v ripple crd_vcc voltage regulated t off t on charge crd_vcc next crd_vcc charge (time is not to scale) when the crd_vcc is programmed to zero volt, or when the card is extracted from the socket, the active pull down q7 rapidly discharges the output reservoir capacitor, making sure the output voltage is below 0.4 v when the card slides across the iso contacts. based on the experiments carried out during the ncn6001 characterization, the best comprise, at time of printing this document, is to use two 4.7 f/10 v/ ceramic/x7r capacitors in parallel to achieve the crd_vcc filtering. the esr will not extend 50 m over the temperature range and the combination of standard parts provide an acceptable ?20% to +20% tolerance, together with a low cost. table 9 gives a quick comparison between the most common type of capacitors. obviously, the capacitor must be smd type to achieve the extremely low esr and esl necessary for this application. figure 18 illustrates the crd_vcc ripple observed in the ncn6001 demo board depending upon the type of capacitor used to filter the output voltage.
ncn6001 http://onsemi.com 23 table 9. ceramic/electrolytic capacitors comparison manufacturers type/series format max value tolerance typ. z @ 500 khz murata ceramic/grm225 0805 10 f/6.3 v ?20%/+20% 30 m murata ceramic/grm225 0805 4.7 f/6.3 v ?20%/+20% 30 m vishay tantalum/594c/593c ? 10 f/16 v ? 450 m vishay electrolytic/94sv ? 10 f/10 v ?20%/+20% 400 m ? electrolytic low cost ? 10 f/10 v ?35%/+50% 2.0 the dc/dc converter is capable to start with a full load connected to the crd_vcc output as depicted in figure 19. in this example, the converter is fully loaded when the system starts from zero. figure 18. typical crd_vcc ripple voltage test conditions: cout = 2x 4.7 f/6 v/ceramic x7r, temp = +25 c iout = maximum specification figure 19. output voltage startup under full load conditions 58 60 62 64 66 68 70 72 74 2.5 3.0 3.5 4.0 4.5 5.0 5 .5 eff(%) figure 20. crd_vcc efficiency as a function of the input supply voltage v bat (v) l out = 22 h/esr = 2 v out = 3.0 v v out = 5.0 v v out = 1.8 v the curves illustrate the typical behavior under full output current load (35 ma, 60 ma and 65 ma), according to emv specifications.
ncn6001 http://onsemi.com 24 during the operation, the inductor is subject to high peak current as depicted figure 21 and the magnetic core must sustain this level of current without damage. in particular, the ferrite material shall not be saturated to avoid uncontrolled current spike during the charge up cycle. moreover, since the dc/dc efficiency depends upon the losses developed into the active and passive components, selecting a low esr inductor is preferred to reduce these losses to a minimum. test conditions: input vcc voltage = 5.0 v current = 200 ma/div tamb = +20 c figure 21. typical inductor current according to the iso7816?3 and emv specifications, the interface shall limits the crd_vcc output current to 200 ma maximum, under short circuit conditions. the ncn6001 supports such a parameter, the limit being depending upon the input and output voltages as depicted in figure 22. on the other hand, the circuit is designed to make sure no over current exist over the full temperature range. as a matter of fact, the output current limit is reduced when the temperature increases: see figure 23. 0 20 40 60 80 100 120 140 160 180 23456 figure 22. output current limits v bat i omax = f (v bat ) v o = 3.0 v v o = 5.0 v v o = 1.8 v i out 100 110 120 130 140 150 160 ?25 ?5 15 35 55 75 95 11 5 temperature ( c) i out (ma) v o = 3.0 v v o = 5.0 v v o = 1.8 v figure 23. output current limit as a function of the temperature
ncn6001 http://onsemi.com 25 smart card clock divider the main purpose of the built?in clock generator is threefold: 1. adapts the voltage level shifter to cope with the different voltages that might exist between the mpu and the smart card. 2. provides a frequency division to adapt the smart card operating frequency from the external clock source. 3. controls the clock state according to the smart card specification. in addition, the ncn6001 adjusts the signal coming from the microprocessor to get the duty cycle window as defined by the iso7816?3 specification. the byte content of the spi port, b2 & b3, fulfills the programming functions when cs is low as depicted in figure 25 and figure 24. the clock input stage (clk_in) can handle a 20 mhz frequency maximum signal, the divider being capable to provide a 1:4 ratio. of course, the ratio must be defined by the engineer to cope with the smart card considered in a given application and, in any case, the output clock [crd_clk] shall be limited to 20 mhz maximum. in order to minimize the di/dt and dv/dv developed in the crd_clk line, the output stage includes a special function to adapt the slope of the clock signal for different applications . this function is programmed by the mosi register (table 2: wrt_reg bits definitions and functions) whatever be the clock division. in order to avoid any duty cycle out of the smart card iso7816?3 specification, the divider is synchronized by the last flip flop, thus yielding a constant 50% duty cycle, whatever be the divider ratio (figure 24 ). consequently, the output crd_clk frequency division can be delayed by four clk_in pulses and the microcontroller software must take this delay into account prior to launch a new data transaction. on the other hand, the output signal duty cycle cannot be guaranteed 50% if the division ratio is 1 and if the input duty cycle signal is not within the 46?56% range. the input signals clk_in and mosi/b3 are automatically routed to the level shifter and control block according to the mode of operation. crd_clk clock_in clock : 2 clock : 4 b2 b3 clock is updated upon these bits program internal clock programming is activated by the b2 + b3 logic state clock = 1:1 ratio clock : 1 figure 24. typical clock divider synchronization clock: 4 rising edge clock divider figure 25. basic clock divider and level shifter b1 b0 b3 b2 clk_in vcc crd_clk crd_vcc level shifter and control programming crd_clk slope note: bits [b0...b3] come from spi data programming crd_clk division sync async sync u1 digital_mux out sel a b
ncn6001 http://onsemi.com 26 the input clock can be divided by 1/1, ? or ? , depending upon the specific application, prior to be applied to the smart card driver. on the other hand, the positive and negative going slopes of the output clock (crd_clk) can be programmed to optimize the operation of the chip (table 10). the slope of the output clock can be programmed on the fly, independently of either the crd_vcc voltage or the operating frequency, but care must be observed as the crd_rst will reflect the logic state present at mosi/b4 register. table 10. output clock rise and fall time selection b0 b1 crd_clk division ratio crd_clk slo_slp crd_clk fst_slp 0 0 ? output clock = low output clock = low 0 1 1 10 ns (typ.) 2 ns (typ.) 1 0 1/2 10 ns (typ.) 2 ns (typ.) 1 1 1/4 10 ns (typ.) 2 ns (typ.) figure 26. force crd_clk to low figure 27. force crd_clk to active mode figure 28. crd_clk programming note: waveforms recorded without external compensation network. figure 29. crd_clk operating low speed (top trace ), full speed (bottom trace)
ncn6001 http://onsemi.com 27 input schmitt triggers all the logic input pins have built?in schmitt trigger circuits to protect the ncn6001 against uncontrolled operation. the typical dynamic characteristics of the related pins are depicted in figure 30. the output signal is guaranteed to go high when the input voltage is above 0.70* v cc , and will go low when the input voltage is below 0.30* v cc . figure 30. typical schmitt trigger characteristic output input v bat on off 0.3 v bat 0.7 v bat v bat security features in order to protect both the interface and the external smart card, the ncn6001 provides security features to prevent catastrophic failures as depicted hereafter. pin current limitation: in the case of a short circuit to ground, the current forced by the device is limited to 15 ma for any pins, except crd_clk pin. no feedback is provided to the external mpu. dc/dc operation: the internal circuit continuously senses the crd_vcc voltage and, in the case of either over or under voltage situation, updates the read_reg register accordingly and forces int pin to low. this register can be read out by the mpu. battery voltage: both the over and under voltage are detected by the ncn6001, the read_reg register being updated accordingly. the external mpu can read the register through the miso pin to take whatever is appropriate to cope with the situation. esd protection the ncn6001 includes silicon devices to protect the pins against the esd spikes voltages. to cope with the different esd voltages developed across these pins, the built?in structures have been designed to handle either 2.0 kv, when related to the microcontroller side, or 8.0 kv when connected with the external contacts. practically, the crd_rst, crd_clk, crd_io, crd_c4, and crd_c8 pins can sustain 8.0 kv, the maximum short circuit current being limited to 15 ma. the crd_vcc pin has the same esd protection, but can source up to 65 ma continuously, the absolute maximum current being internally limited to 150 ma. printed circuit board layout since the ncn6001 carries high speed currents together with high frequency clock, the printed circuit board must be carefully designed to avoid the risk of uncontrolled operation of the interface. a typical single sided pcb layout is provided in figure 32 highlighting the ground technique. dual face printed circuit board may be necessary to solve ringing and cross talk with the rest of the system.
ncn6001 http://onsemi.com 28 figure 31. ncn6001 engineering test board schematic diagram test board schematic diagram u2 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 v cc v cc v cc v cc 22 h l1 r7 47 k 10 f c2 gnd gnd q1 r4 2.2 k d4 gnd gnd gnd gnd r8 47 r tp1 tp3 tp5 tp7 tp2 tp4 tp6 tp8 tp11 tp12 tp14 tp9 tp13 tp10 crd_vcc 2n2222 gnd r6 47 k c3 22 pf 4.7 f c7 swa swb i/o rst clk c4 c8 v cc gnd i/o clk_in miso clk_sp v cc mosi en_rpu loutl crd_det crd_io crd_rst crd_clk crd_vcc c4/s0 c8/s1 pwr_gnd louth gnd r9 1 k gnd gnd r5 4.7 k clk_sel j5 demo board identify ncn6001 j1 10 f c1 gnd r1 2.2 k gnd d1 cs clk_sp1 mosi miso i/o int v cc gnd iso7816 11 10 7 2 3 4 8 1 5 18 20 19 17 13 15 14 16 11 12 6 10 4 5 8 7 3 2 1 9 int cs tp15 gnd j9 ground 2 11 int i/o clk_in cs miso clk_sp mosi 4.7 f c8 j4 smartcard_d crd_det crd_io rst clk rst c4 c8 v cc see note see note control and i/o p1 ex_clk v cc note: capacitor c2 and resistor r8 are adjusted at final checkout. depending upon the pcb layout, these two components may or may not be necessary.
ncn6001 http://onsemi.com 29 component side (top) copper side (bottom) top side figure 32. ncn6001 demo board printed circuit board layout
ncn6001 http://onsemi.com 30 table 11. demo board bill of material desig. part type footprint description supplier part number c1 10 f 1206 capacitor murata grm40?x5r?106k6.3 c2 10 f 1206 capacitor murata grm40?x5r?106k6.3 c3 22 pf 805 capacitor murata c7 4.7 f 1206 capacitor murata grm40?034x5r?475k6.3 c8 4.7 f 1206 capacitor murata grm40?034x5r?475k6.3 d1 v cc sip2 led diode radio spares 180?8467 d4 crd_vcc sip2 led diode radio spares 180?8495 j1 control & i/o idc50 fujitsu fcn?704q050?au/m j4 smartcard smartcard_iso smart card connector fci 7434?l01?35s01 j5 clk_sel sip3 connector j9 ground gnd_test connector l1 22 h 1008 inductor coilcraft 1008ps?223?m p1 ex_clk smb smb connector radio spares 112?2993 q1 2n2222 to?18 npn on semiconductor r1 2.2 k 805 radio spares r4 2.2 k 805 radio spares r5 4.7 k 805 radio spares r6 47 k 805 radio spares r7 47 k 805 radio spares r8 47 r 805 radio spares r9 1.0 k 805 radio spares tp1 clk_in test_point test_point radio spares 203?4910 tp10 rst test_point test_point radio spares 203?4910 tp11 clk test_point test_point radio spares 203?4910 tp12 c4 test_point test_point radio spares 203?4910 tp13 c8 test_point test_point radio spares 203?4910 tp14 vcc test_point test_point radio spares 203?4910 tp15 gnd test_point test_point radio spares 203?4910 tp2 int test_point test_point radio spares 203?4910 tp3 i/o test_point test_point radio spares 203?4910 tp4 cs test_point test_point radio spares 203?4910 tp5 miso test_point test_point radio spares 203?4910 tp6 clk_spi test_point test_point radio spares 203?4910 tp7 mosi test_point test_point radio spares 203?4910 tp8 det test_point test_point radio spares 203?4910 tp9 crd_io test_point test_point radio spares 203?4910 u1 ncn6001 on semiconductor 13. all resistors are 5%, ? w , unless otherwise noted. all capacitors are ceramic, 10%, 6.3 v, unless otherwise noted.
ncn6001 http://onsemi.com 31 figure 33. typical multiple parallel interfaces 12 13 20 18 gnd 9 1 2 3 4 5 7 8 6 10 19 17 16 15 14 11 swa swb c8 c4 clk rst v cc gnd i/o 17 18 7 4 3 2 1 5 8 iso7816 gnd gnd 10 f u1 clk_spi clk_in mosi en_rpu miso cs lout_h gnd crd_vcc crd_clk crd_io lout_l crd_rst crd_det c8/s1 c4/s0 v cc i/o int v cc pwr_gnd gnd c2 10 f c1 strobe_async strobe_sync ncn6001 22 h l1 multiple smart card reader 12 13 20 18 9 1 2 3 4 5 7 8 6 10 19 17 16 15 14 11 swa swb c8 c4 clk rst v cc gnd i/o 17 18 7 4 3 2 1 5 8 iso7816 gnd u2 clk_spi clk_in mosi en_rpu miso cs lout_h gnd crd_vcc crd_clk crd_io lout_l crd_rst crd_det c8/s1 c4/s0 v cc i/o int pwr_gnd gnd c2 10 f ncn6001 22 h l2 12 13 20 18 9 1 2 3 4 5 7 8 6 10 19 17 16 15 14 11 swa swb c8 c4 clk rst v cc gnd i/o 17 18 7 4 3 2 1 5 8 iso7816 gnd u3 clk_spi clk_in mosi en_rpu miso cs lout_h gnd crd_vcc crd_clk crd_io lout_l crd_rst crd_det c8/s1 c4/s0 v cc i/o int pwr_gnd gnd c2 10 f ncn6001 22 h l3 12 13 20 18 9 1 2 3 4 5 7 8 6 10 19 17 16 15 14 11 swa swb c8 c4 clk rst v cc gnd i/o 17 18 7 4 3 2 1 5 8 iso7816 gnd u5 clk_spi clk_in mosi en_rpu miso cs lout_h gnd crd_vcc crd_clk crd_io lout_l crd_rst crd_det c8/s1 c4/s0 v cc i/o int pwr_gnd gnd c2 10 f ncn6001 22 h l4 v cc v cc v cc v cc 12 13 20 18 9 1 2 3 4 5 7 8 6 10 19 17 16 15 14 11 swa swb c8 c4 clk rst v cc gnd i/o 17 18 7 4 3 2 1 5 8 iso7816 gnd u4 clk_spi clk_in mosi en_rpu miso cs lout_h gnd crd_vcc crd_clk crd_io lout_l crd_rst crd_det c8/s1 c4/s0 v cc i/o int pwr_gnd gnd c6 10 f ncn6001 22 h l5 v cc microcontroller smartcard j5 asynchronous asynchronous asynchronous smartcard smartcard asynchronous smartcard asynchronous smartcard address = $0 3 address = $0 2 address = $0 1 address = $0 0 the five interfaces share a common microcontroller bus, a bank of four ncn6001 supporting asynchronous card with a dedicated cs line, the fifth one being used by to the synchronous or asynchronous transactions with a unique cs line. on the other hand, the only activated i/o pullup resistor shall be one of the asynchronous bank.
ncn6001 http://onsemi.com 32 abbreviations lout_l and lout_h dc/dc external inductor cout output capacitor class a 5v smart card class b 3v smart card crd_c4 interface ic card digital control crd_c8 interface ic card digital control crd_clk interface ic card clock input crd_det card insertion/extraction detection crd_io interface ic card data link crd_rst interface ic card reset input crd_vcc interface ic card power supply line crd_v cc card power supply input cs parasitic stray capacitance cs chip select emv europay master card visa fst_slp crd_clk fast slope (t r and t f ) gie?cb groupement inter economique ? carte bancaire icc current at card v cc pin int interrupt iso international standards organization c microcontroller miso master in slave out: data from the interface mosi master out slave in: data from the external microcontroller nc normally close no normally open por power on reset rfu reserved future use spi serial port interface t0 smart card data transfer procedure by bytes t1 smart card data transfer procedure by strings slo_slp crd_clk slow slope (t r and t f ) vcc mpu power supply voltage ordering information device package shipping ? ncn6001dtbr2g tssop?20 (pb?free) 2,500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncn6001 http://onsemi.com 33 package dimensions tssop?20 case 948e?02 issue c dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. 110 11 20 pin 1 ident a b ?t? 0.100 (0.004) c d g h section n?n k k1 jj1 n n m f ?w? seating plane ?v? ?u? s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 --- --- s u 0.15 (0.006) t 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncn6001/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.

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